On Intel’s Architecture Day 2020, the company revealed that the upcoming Intel Tiger Lake processors will be based on the 10nm SuperFin process. Unlike the current Ice Lake processors which are based on 14 nm node, the Tiger Lake CPUs will be manufactured on the company’s 10nm SuperFin process which allows them to reach 14nm-level clocks along with other major architectural improvements.
Some Tiger Lake processors will be able to hit 5 GHz clocks. The Tiger Lake processors will come with a revamped 10nm SuperFin transistor technology, a rebalanced cache hierarchy to improve performance, dual ring bus fabric, new security enhancements, support for LPDDR5-5400 in the future, PCIe gen 4.0 and Xe LP (Low Power) graphics. At release time, the Tiger Lake processors will support LP4x-4267 until LPDDR5 is available.
SuperFin was developed by Intel to fix the inability to sustain high clock rates in the Sunny cove 10nm architecture. Now, Tiger lake will use Willow cove cores which doubles the bandwidth and shifts to a double ring architecture. Tiger Lake processors will also ship with the first Xe iGPU, which is capable of achieving 2.6 teraflops of performance, which is huge for a mobile chip.
The SuperFin process transistors feature a new thin barrier which decreases the interconnect resistance by about 30%. Intel’s Vice President of Client Engineering Group, Boyd Phelps showed off the SuperFin transistors during the Intel Architecture day presentations. Talking about the Architectural Improvements, Boyd Phelps said:
We added a new high-performance transistor that increases drive current with an improved gate process enabling higher mobility while also lowering the source drain resistance and we did this all with lower capacitance. Not only do we add a new device for high performance. But we also took our existing high VT devices used in our non-high frequency critical IPS, like Type-C, PCIe, Imaging and made them more efficient. We were able to speed those devices up while lowering their leakage and this gave us the ability to lower their operating voltage returning yet more power headroom to be available for our high-performance IPS.
Intel says that the biggest performance gain comes not from using Willow cove cores, but the dynamic frequency range of the 10nm SuperFin transistors. They are capable of running at higher clocks while using low voltage. Intel also gains an upper hand over AMD’s Renoir APUs, which only support PCIe gen 3.0, while Tiger Lake will support PCIe gen 4.0.
We will have to wait for the Intel Tiger Lake processors to come out to see how they perform with the new 10nm Superfin and stack against AMD chips, which currently have the upper hand in performance.
