After announcing the Tiger Lake mobile CPUs at Intel Architecture Day 2020, Intel has revealed more information about the next generation of mobile CPUs at Hot Chips 2020 including a picture of its die. At Intel’s Architecture Day, the company revealed that the upcoming Tiger Lake processors will be based on the 10nm SuperFin process.
At Hot Chips 2020, Intel has revealed some more and detailed information about the Tiger Lake chips, including pictures of a quad-core Tiger Lake die. Intel has also disclosed more information about the Integrated Xe graphics which will be part of the Tiger Lake CPUs. According to some leaked benchmarks, Intel’s Tiger Lake Xe integrated graphics beat the Vega 11 chipset in Ryzen 4000 mobile by a sizable 35-percent margin.
The die for a Tiger Lake Quad-core CPU has also shown by Intel which gives more information about the interconnection between the cores, which has been greatly enhanced the ring bus connection. The upcoming Tiger Lake chips will be Intel’s 11th Generation of mobile processors, which will be based on the new Willow Cove architecture that is built on the new 10nm SuperFin transistors.
Intel claims that the SuperFin transistors will offer higher, consistent frequency speeds while drawing low power. The processors will also feature increased cache capacities and will support LPDDR5-5400 memory and PCIe gen 4.0.
A highlighted image was shared by @Locuza_ which showed a detailed explanation of a Tiger Lake chip die.
The die shows the complete breakdown of the Tiger Lake processor die. We can see the placement of L1, L2, and L3 cache structure along with the different Processing units. Intel has increased capacity for its L2 (MLC) and L3 (LLC) caches, which now weigh in at 1.25MB and 12MB.
A big feature of Tiger Lake architecture is the Xe Integrated graphics as it goes above and beyond in performance from the Ryzen ‘Renoir’ 4000 series, which has the Vega 11 graphics. The Xe Low Powered (LP) GPU enjoys the same benefits from Intel’s redesigned FinFET transistors and SuperMIM capacitors included in the Tiger Lake CPU.
It provided stability across a greater range of voltages and a higher frequency uplift across the board. The Xe LP features 96 execution cores which are greater than the Iris G7’s 64 cores. On top of that, each of the execution units has FP/INT Arithmetic Logic Units twice as wide as Iris+ G7. An increase in L3 cache to 16MB really shows what a massive jump the Xe graphic will provide.
